1. Field of the Invention
The present invention relates to a counter circuit, and more particularly to a counter circuit having an addition function and/or a subtraction function, which is applicable to an address generator or a general counter.
2. Description of the Prior Art
With the advance of a large scale integrated circuit (LSI) technology, a microprocessors capable of a high-speed operation has been provided. Such microprocessors are required in a field of complex data processing, for example, signal processing. A signal processor can be used to manipulate a large amount of data, such as voice or image data. Specific operations such as the fast Fourier transform (FFT) operations and filtering operation are often required, in which both successive data access and non-successive data access are operatively used. Successive data access is performed by a well known program counter in which the content (counted value) is incremented or decremented count by count. However, non-successive data access requires a complex hardware circuit.
In detail, the FFT operation employs a product-sum operation which is accomplished in the prior art by storing a plurality of data in a memory (e.g. RAM) and by retrieving two units of data at a predetermined time interval. The retrieved data are multiplied together by a multiplier. Each product produced by the multiplier is integrated (accumulated), sequentially.
In this operation, two kinds of data access operations are operatively used. One is the successive data access operation by which two units of data are retrieved from two successive address locations of the memory. The other is the non-successive data access operation by which data from non-successive address locations of the memory are retrieved. The former is performed by using the program counter as mentioned above. I contrast, the prior art, the latter requires a specific address counter. Such address counter, for instance, must produce an address which is incremented or decremented by 2.sup.n. The program counter of the prior art can not produce non-successive addresses by itself. Therefore, an adder or a subtracter is required to produce the non-successive addresses.
However, address production by means of the adder or the subtractor requires a long period of time and is unsuitable for signal processing operations which require high-speed operation. Further, since the adder or the subtractor was provided independently of the product-sum operating unit, the number of hardware elements to be employed in the signal processor was increased. Thus, it becomes difficult to form the signal processor on a single semiconductor chip.
Non-successive data production is required not only in the address operation but also in numerical operations or general (or special) purpose digital data operations. The counter of the prior art has not been successful in increasing the speed of operation beyond a certain limit determined by the technology of the adder or the subtracter.
It is an object of the present invention to provide a counter circuit which can produce non-successive data at a high-speed.
It is another object of the present invention to provide a novel counter which can operatively produce successive and non-successive data.
Still another object of the present invention is to provide a counter circuit which can be formed on a signal processor chip with a small size.